A digital-to-analog converter (DAC) is one of the common and important elements used in current analog integrated circuitry. Particularly for a communication system including analog IC circuitry, the performance of the communication system highly depends on the quality of the DAC design. One type of DACs, e.g. current steering DACs, is adapted for high-speed and high-resolution digital-to-analog conversion in IC circuitry of a communication system.
Please refer to FIG. 1A, in which a differential current steering DAC is shown. The DAC includes a current source Iin, two PMOS transistors P1 and P2, and two resistors R1 and R2, wherein the current source is coupled between a first voltage source Vdd and a node “a”; the sources of the transistors P1 and P2 are coupled to the node “a”; the gates of the transistors P1 and P2 are coupled to control signal ends C1 and C2, respectively; the drains of the transistors P1 and P2 are differential voltage output terminals V+ and V−; the resistor R1 is coupled between the drain of the transistor P1 and a second voltage source Vss; the resistor R2 is coupled between the drain of the transistor P2 and the second voltage source Vss; the resistors R1 and R2 have equal resistance; and the second voltage source Vss is typically of ground voltage. The DAC as shown in FIG. 1A has a differential architecture and is capable of eliminating common mode noise.
The control signal ends C1 and C2 respectively receive complement digital signals for controlling the transistors P1 and P2 to turn on or turn off. For example, when the control signal at the control signal end C1 turns on the transistor P1, current flows through the resistor R1 so as to generate analog voltages at the differential voltage output terminals V+ and V−. On the other hand, when the control signal at the control signal end C2 turns on the transistor P2, current flows through the resistor R2 so as to generate analog voltages at the differential voltage output terminals V+ and V−.
Please refer to FIG. 1B, which illustrates waveforms of control signals at the control signal ends C1 and C2. Since the control signals are complementary to each other, the control signal at the end C2 is at a low level, e.g. Vss, while the control signal at the end C1 is at a high level, e.g. Vdd. On the other hand, the control signal at the end C2 is at a high level, e.g. Vdd, while the control signal at the end C2 is at a low level, e.g. Vss. Since the current steering DAC as shown in FIG. 1A is implemented with P-type transistors, the high level is a turn-off voltage while the low level is a turn-on voltage.
In the above-described current steering DAC, the turn-off voltage and the turn-on voltage are implemented with the first voltage source Vdd and the second voltage source Vss, respectively. Accordingly, the voltage difference between the high level (Vdd) and the low level (Vss) is too large to achieve a satisfactory operating speed. In addition, a drawback of too much noise would be rendered.
Please refer to FIG. 1C, which illustrates the circuitry of a single-ended current steering DAC. The current steering DAC includes a current source Iin, two PMOS transistors P1 and P2 and a resistor R1. The current source Iin is coupled between a first voltage source Vdd and a node “a”; the sources of the transistors P1 and P2 are coupled to the node “a”; the gates of the transistors P1 and P2 are respectively coupled to a control signal end C1 and a reference voltage Vref; the drain of the transistor P1 is coupled to a second voltage source Vss; the drain of the transistor P2 is coupled to a voltage output end Vout; and the resistor R1 is coupled between the drain of the drain of the transistor P2 and the second voltage source Vss. Since the current steering DAC is single-ended, the second voltage source (Vss) is typically ground voltage. Furthermore, the control signal end may receive a digital signal which is referred to so as to turn on or turn off the transistor P1, and thereby generates an analog voltage at the voltage output end Vout.
Please refer to FIG. 1D, which illustrates the waveform of the control signal at the control signal end C1. Since the control signal is digital, the high level is a turn-off voltage while the low level is a turn-on voltage.
In the above-described current steering DAC, likewise, the turn-off voltage and the turn-on voltage are implemented with the first voltage source Vdd and the second voltage source Vss, respectively. Accordingly, the voltage difference between the high level (Vdd) and the low level (Vss) is too large to achieve a satisfactory operating speed. In addition, a similar drawback of too much noise would be rendered.
In order to enhance operating speed and reduce noise, U.S. Pat. No. 6,369,734 discloses method and apparatus for increasing linearity and reducing noise coupling in a digital to analog converter, as shown in FIG. 2. The DAC includes transistors 402, 404 and 406, wherein from the gates of the transistors 404 and 406, a pair of complementary control signals are inputted. In the DAC, a bias circuit 430 is provided and includes a resistor divider consisting of resistors 416 and 418. The resistor divider divides a voltage source Vdd and the divided voltage Va is outputted through a voltage buffer 414, wherein Va=Vdd*R418/(R416+R418) where R418 is the resistance of the resistor 418 and R416 is the resistance of the resistor 416. Furthermore, the voltage source Vdd and the divided voltage Va are coupled to the power inputs of the Not Gates 408 and 410. In other words, the high level of the Not Gates 408 and 410 will be equal to the voltage source Vdd while the low level will be equal to the divided voltage Va. It is also understood from the above descriptions that the high level of the control signal, i.e. turn-off voltage, is equal to the power voltage Vdd, and the low level, i.e. turn-on voltage, is equal to the divided voltage Va. Accordingly, the voltage difference between the high level and the low level of the control signal decreases so as to enhance the operating speed of the DAC and reduce noise.
FIG. 3A and FIG. 3B illustrate two further bias circuits disclosed in U.S. Pat. No. 6,369,734. Either of the two bias circuits may be used to replace the bias circuit 430 in the DAC of FIG. 2.
In the bias circuit 430 of FIG. 3A, a diode 450 has its N-type side grounded. Since there is a certain voltage drop, e.g. 0.6V, between the P-type side and the N-type side of the diode 450, the voltage source Vdd and the P-type side voltage Vp are coupled to the power inputs of the Not Gates 408 and 410. In other words, the high level of the Not Gates 408 and 410 will be equal to the voltage source Vdd while the low level will be equal to the P-type side voltage Vp.
In the bias circuit 430 of FIG. 3B, a divider circuit consisting of a P-type transistor 452 and an N-type transistor 454 is provided to generate a divided voltage Vb. The voltage source Vdd and the divided voltage Vb are coupled to the power inputs pf the Not Gates 408 and 410. In other words, the high level of the Not Gates 408 and 410, i.e. turn-off voltage, will be substantially equal to the voltage source Vdd while the low level, i.e. turn-on voltage, will be substantially equal to the divided voltage Vb.
U.S. Pat. No. 6,414,618 also discloses a digital to analog converter with reduced ringing for enhancing operating speed and reducing noise, as shown in FIG. 4A. The DAC includes transistors 170, 172, 174 and 176 and resistors 178 and 180, wherein the transistors 170 and 172 serve as a current source. The DAC further includes transistors 182, 184, 188 and 190 serving as a switch for providing a digital control signal, e.g. with a high level Vref1 serving as a turn-off voltage or with a low level Vref2 serving as a turn-on voltage, to the gates of the transistors 174 and 176. A bias circuit of the DAC includes transistors 162, 164, 166 and 168 connected between voltage sources Vdda and Vssa in series, wherein the transistors 166 and 168 are arranged in diode connection. In this case, the low level Verf2 is about 0.6V+Vssa and the high level Vref1 is about 1.2V+Vssa. Accordingly, the reduced voltage difference between the high level and the low level of the control signal results the enhancement of the operating speed of the DAC and the reduction of noise.
FIG. 4B illustrates the waveform of the control signal in the DAC of FIG. 4A. Since the control signals inputted into the gates of the transistors 174 and 176 are complementary digital signals, the high level Vref1 of the control signal serves as a turn-off voltage and the low level Vref2 serves as a turn-on voltage.
It is understood that the operating speed of the DAC can be enhanced and noise can be reduced by reducing the voltage difference between the high level and the low level of the control signal. However, once the DAC and the bias circuit are produced, the high level and the low level of the control signal are unchangeable and cannot be modified with practical design. If the IC circuitry has any shift during manufacturing, a preset constant low level (turn-on voltage) would not be proper anymore as there are one or more PMOS transistors entering a triode region. Then the operating speed of the DAC will be adversely affected and the preferable swing range cannot be found because the best bias is not well located.
For example, referring again to FIG. 4A, when the low level (turn-on voltage) of the DAC is too low, the PMOS transistors 174 and 176 will enter a triode region. On the other hand, if the low level (turn-on voltage) of the DAC is too high, the PMOS transistor 172 included in the current source will enter a triode region. Accordingly, the operating speed of the DAC will be deteriorated and non-linear distortion will be rendered.